International Supercomputing Conference 2015 – a researcher’s wrap-up

ISC 2015 (Franfurt a.M. / Germany) celebrated an anniversary to the conference. Although some standard contributors were absent this year due to political reasons, American and German attendance still peaked.

Research-wise, Exascale Computing was still an omni-present topic (6 talks alone on this topic). The given computing limit is approached from several perspectives: On the software side, researchers take care to further optimize communication, computation and data usage (M. Schulz, LLNL). New computing models appear that address Exascale Computing for Data-driven applications (web-media demands), outside the classic demands of numerical method solvers.  Architecture-wise, a component-based bulding block model comprising technologies such as 3D stacked memory (amongst others) presents a step-by-step approach to the exascale barrier(H. Simon, LBNL). Third (and from my personal perspective most exciting) is the more and more common use of MIC- and GPU accelerators, particularly in the top 10 of HPC clusters (contradicting Mr Sterling’s claim of disappearing accelerator use within the Top500). It should be noted that even at ISC 2015, talks on FPGA acceleration has been given, which are also accelerators to some extend. Every accelerator attachment comes with its drawbacks, while it is the researcher’s and engineer’s design challenge to hide the drawbacks and take full benefit of the advantages. The announcement of developing a „domestic accelerator“ in China by Yutong Lu, based on the well-known ARM architecture (similar to ARM Cortex-based mobile processors), is exciting and, for the european spectator, unexpected. I am personally interested in this new chip, but as some of my colleagues I have minor doubts. It took Intel 3 iterations of SCCC (Single-chip Cloud Computing) redesign (Larrabee, Larrabee 2, Intel MIC XeonPhi) in order to achieve acceptable performance gains with the chip while maintaining common multicore SMP programmability via OpenMP. Hence, the „domestic accelerator for China“ is a daring move. I wish the researchers good fortune along their design path.

Intel as well as numerical computing research groups presented their newest advances and iterations of Linear Algebra packages (K. Pamnany et al., K. Kabir et al.), particularly focussing on accelerator benefits using Level-3 generalized matrix multi (GEMM).

Selected talks discussed advances and envisaged usage of Quantum Computers, as well as the clearification of recent challenges on the topic.

Of particular interest was, from my perspective, the special session on Advanced Display & Visualization Technologies. The discussed topics covered the use of large-scale projector systems, interaction paradigms for large display walls in different use case setups, and the development of Virtual Reality (VR) for exploring scientific datasets. A great session and very inviting talks with the presenting researchers after the session. Felt like „home again“, scientifically. Myself, I presented a first study of Ms Varbanescu’s and my work on semi-automatic visual content indexing of massive media archives, majorly by theoretically exploiting stochastic effects of Convolutional Neural Networks and practically embedding the work on accelerator-powered clusters, such as the DAS-4.

Dieser Beitrag wurde unter Allgemein, English, HPC, Work veröffentlicht. Setze ein Lesezeichen auf den Permalink.